The DDR memory subsystem (DDR controller, PHY and IO) is critical to the successful operation of a SoC. System performance and field reliability demand that the DDR subsystem implementation offer the highest performance while at the same time offering the highest quality, in combination with a small footprint and minimal power consumption.
Uniquify offers a complete set of silicon-proven IP for implementing DDR4/3 and LPDDR4/3/2 subsystems in 14/22/28/40/55nm processes, including 14nm FinFET and 22nm FD-SOI, from multiple foundries.
Uniquify’s patented Self-Calibrating logic (SCL), Dynamic Self-Calibrating Logic (DSCL), Adaptive Bit Calibration (ABC), and Dynamic Adaptive Bit Calibration Logic (DABC) technologies automatically adjusts the DDR interface timing at power up and dynamically during system operation to mitigate both static and dynamic variations. This allows each system to achieve the highest possible DDR performance with the smallest area and lowest power without sacrificing reliability. The SCL, DSCL, ABC, and DABC technologies are covered by 18 U.S. patents and are embedded within Uniquify’s DDR PHY and operate seamlessly. Uniquify’s DDR PHY (including SCL, DSCL, ABC, and DABC) utilizes the technologies protected by US Patents 7,975,164; 8,661,285; 8,843,778; 8,990,607; 9,021,293; 9,081,516; 9,075,543; 9,552,853; 9,300,443; 9,584 309; 9,431,091; 9,805,784; 10,229,729; 10,032,502; 10,242,730; 10,269,408. Additional patents may be pending in the U.S. and elsewhere. No other DDR IP on the market offers this breakthrough technology.