Product Highlights
- Complete DDR3 solution including memory controller, DFI PHY physical interface, digital DLL, AXI/AHB bus interface
- Patent-pending automatic Self-Configuring Logic (SCL) technology eliminates system level timing issues
- Low read data capture latency
- Fast turn-around time between read and write operations
- Optimum design closure through DFI PHY macros
- Chip/system yield improvement through SCL (DFY)
- Embedded chip/system testability (DFT)
- Parameterizable data bus and ECC width
- Deep command pipeline support
- Support for built in read-modify-write
- Fully configurable ODT window
- Backwards compatible with DDR2 Memory Controller
Block Diagram
Nethra Imaging procured Uniquify’s DDR3 IP and physical implementation services for our highly complex SoC designs because of their proven and disciplined 65nm/40nm ASIC methodology, Perseus. Uniquify’s dedicated team exceeded our expectations by meeting our stringent tapeout schedule and implementing all complex SoC requirements. We look forward to developing a great partnership with Uniquify for our upcoming multi-million SoC designs.
