Uniquify - ASIC Design & IP Solutions

Perseus: 65nm/40nm/32nm Proven ASIC Design Flow

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Uniquify has developed a customer proven automated design flow, Perseus, which enables predictable tape-out schedules, and mananges risk mitigation of today’s most complex 65nm/40nm/32nm SoC designs. Perseus seamlessly integrates various EDA design environments including, Magma, Synopsys, Cadence and Mentor Graphics. Structured library and design reviews identify and fix common design or flow problems ahead of implementation to improve efficiency and quality of results. This unique design methodology has proven to shorten design cycles while ultimately ensuring first time working silicon through a more convergent design flow.

Perseus Environment


 

 

 When Foveon, Inc. searched for a services partner to work on our next-generation Image Sensor solutions, we selected Uniquify because of their proven full-cip tapeout record, experience with special mixed-signal processes and ability to successfully tackle tough design challenges while meeting our aggressive schedule requirements. Uniquify delivered for us. We would use them again for sure.

Andrew Cole, VP Sensor Development, Foveon Inc.