UniquiPHY™ – DFI Compatible DDR PHY with Adaptive Technology
The SoC to DDR SDRAM memory interface is typcially the highest speed bus in a system. A simple intermittent failure in this interface can render a system useless. Failures in the DDR memory subsystem can come from many different causes, but most are due to either static variations in the various system components or from dynamic variations due to the environment the system is operating in.
Uniquify has innovated, developed and embodied adaptive technologies (dynamic self-calibrating logic and dynamic adaptive bit calibration) in its UniquiPHY family of DFI compatible DDR PHYs. The UniquiPHY family delivers the highest performance, smallest footprint, lowest power DDR PHYs available today while at the same time delivering higher system reliability, improved yield and automated, fast DDR system bring-up. This is accomplished by building in patented circuitry and algorithms into the PHY that automatically calibrate the timing interface between the host SoC and the DDR SDRAM during system power-up and continuously during system operation.
SoCs are often designed to go into multiple systems potentially aimed at different markets and applications. Multiple sources may be required for the DDR SDRAM components and PCB boards and SoC packages may also be different. No two components are ever exactly alike – each component has its own unique characteristics that are the result of imperfections (however small) in the manufacturing process. As a result, it is difficult or impossible to determine the exact timing parameters for a given system.
In the first generation of DDR devices, the interface timing margins were relatively wide with a typical allowable timing window of 2.5ns. Even with the variations in the system components, designers were generally able to come up with solutions that could operate comfortably within the allowable timing window. For DDR4, however, the allowable timing window margins drops to about 300ps (more than an 8x reduction). This makes the job of designing the DDR interface extremely challenging as the allowable margin for error is so small.
The JEDEC DDR specifications provide many useful options and techniques for verifying and optimizing the timing interface between the DDR SDRAM and the host device. However, the JEDEC spec does not address the most difficult aspect of timing which is often called the round-trip timing problem or the clock domain crossing problem.
Simply stated, the clock domain crossing problem is the uncertainty in both phase and latency between the DDR clock (DQS strobe) and the SoC system clock during a DDR read operation. Both the phase and latency are different for each system and are dependent on both static component variations as well as dynamic variations due to the operating conditions. It is impossible to accurately predict in advance what these variations will be for a given system.
Today, designers address this issue by going through a lengthy chip bring-up phase where they measure the timing on many different bench samples and then use this data to program delay registers that compensate for both the phase and latency. Of course, the data is based on a finite sample and there is no guarantee that the derived values will work for all systems all the time.
Traditional Approach Cannot Dynamically Adjust to Changing System Conditions
UniquiPHY Adaptive Technology – DSCL
This is where the concept of UniquiPHY comes into play. The concept recognizes that no two systems will ever be exactly alike nor is it possible to predict in advance the operating environment that a system will be placed in. Instead of trying to predict the behavior of the system, adaptive IP accurately measures the behavior of the system during system operation and uses that information to adjust the system parameters as needed to keep the system running reliably.
UniquiPHY’s patented dynamic self-calibrating logic (DSCL) technology is a prime example of the application of adaptive IP in solving the clock domain crossing problem in the SoC to DDR interface.
A very small amount of specialized circuitry in the DDR PHY automatically measures the round trip timing between the SoC and the DDR SDRAM. This is accomplished with almost no impact on memory bandwidth –and the frequency of operation is programmable. After measurement, internal adjustments are automatically made to compensate for any shifts in phase relationship or latency between the DDR SDRAM clock (DQS strobe) and the SoC system clock. This allows us to run the DDR interface reliably and achieve very high performance.
DSCL Automatically Adjusts DDR Capture Point During System Operations
Almost all other approaches to solving the clock domain crossing problem make use of a FIFO to do the synchronization. Not only does this approach introduce latency into the system, it also cannot accommodate more than +/- ½ cycle of timing variation. In addition it requires accurate gate training to make sure that the FIFO clock is enabled at the right time in order to avoid clocking in bad data.
The DSCL approach does not use a FIFO and results in very low latency. In addition, the DSCL approach is able to correct for a much wider range of variation – up to +/- 4 cycles of variation. This wider range is very important for higher speed memory interfaces being implemented in leading edge process technologies where it is quite possible to see multiple cycles of latency between DQS and the system clock.
UniquiPHY Adaptive Technology – DABC
Whereas DSCL manages timing variations and corrections at the byte-lane level, dynamic adaptive bit calibration (DABC) manages and dynamically corrects for intra-byte lane skew. There is only one clock associated with each byte lane and in an ideal world, all bits are aligned and arrive at the same time. In practice this is difficult to achieve and without careful design there is readily noticeable skew between the data bits in the byte lane. This impacts the quality and robustness of the DDR “eye” which is critical to delivering a high quality, highly reliable DDR subsystem.
Bit-bit skew in the byte lane – without dynamic adaptive bit calibration
Dynamic adaptive bit calibration is another adaptive technology that is an integral component of the UniquiPHY DDR PHY IP. DABC automatically and dynamically re-aligns the bit timing within the byte lane to eliminate bit-bit skew. This results in a much cleaner eye, helps support higher performance and delivers a more robust and reliable DDR interface.
Adaptive DABC Technology Eliminates Bit-Bit Skew
The inclusion of adaptive technology in the UniquiPHY DDR IP family brings numerous benefits. These include delivering the highest possible DDR performance, the smallest area and lowest power consumption. In addition, SCL/DSCL provide enhanced system reliability since the operating parameters of the DDR timing interface are being optimized during system operation. And, since SCL/DSCL can compensate for a wide range of both static and dynamic variations it also helps to increase device yield. Finally, the use of adaptive IP simplifies and streamlines the chip bring-up task. Instead of having to test and measure many bench samples (over days or weeks) in order to calibrate the DDR timing interface, SCL and DSCL do it quickly and automatically in just a few minutes.