Product Overview

Register for Uniquify’s DDR Webinars HERE!

Uniquify offers the highest performance, smallest, lowest power DDR subsystem IP available today. Our patented “Dynamic Self-Calibrating Logic” (DSCL) technology and “Dynamic Adaptive Bit Calibration” (DABC) technologies allow our DDR subsystem to not only to deliver the highest possible DDR performance, with a small footprint and low power but also delivers enhanced system reliability and improved device yield. This is achieved by automatically re-calibrating the DDR timing interface on-the-fly during system operation mitigating memory issues due to system operating temperature or voltage drift and allows us to extract the best possible performance out of the DDR subsystem.

Our DDR subsystem IP offering includes a highly flexible and configurable DDR memory controller, a DFI-compliant PHY that incorporates our patented DSCL and DABC technologies and high-performance DDR IOs. All of these IP components may be licensed together or separately depending on the requirement and application.


Uniquify DDR Subsystem IP

 Uniquify’s DDR Subsystem IP

Our DDR IP offerings include:

* DDR2/3/4
* LPDDR2/3/4 (L/UL)

A wide variety of process technologies are supported including:

* 28nm
* 40nm
* 65nm
* 90nm

The DDR controller is delivered as soft IP and is highly configurable as to the number and type of ports, arbitration scheme(s), data bus and ECC width and many other parameters. The PHY is supplied as a hardened block, optimized for the target SoC layout and padframe with many different layout options. The PHY and IO can be delivered as a single, hardened top-level block if requested.

Flexible PHY Layout Options

 Flexible PHY Layout Options – Designed to Match Your Specific Layout Requirments

The DSCL and DABC technologies embedded in the PHY provide an automatic mechanism for precise calibration of the DDR timing interface both at system start-up and during system operation. DSCL and DABC are able to perform a highly accurate measurement of the DDR subsystem timing which is specific both to the system and the operating environment. These patented technologies also simplify the PHY design by removing the need for a FIFO and associated circuitry that are typically required to synchronize the DDR clock (DQS) and the system clock. As a result of this simplification we are able to deliver a DDR solution that is smaller, faster and uses less power. In addition to these benefits DSCL and DABC also deliver enhanced system reliability, much faster system bring-up and improved device and system yield.

Contact us for more info.

"At current process nodes even minor variations in the foundry process can cause timing parameters to drift, which will produce significant yield loss in volume production. SCL automatically accommodates normal process variation--without yield loss--by continuously modifying timing parameters at every power-up. Even system-level aging, which can alter board-level trace delays over years of use, can be accommodated by SCL, thereby improving overall system reliability."
Mahesh Gopalan, VP and Chief Architect DDR Solutions, Uniquify