Resources & Solutions

ASIC designers in sub-90nm era are faced with many barriers caused by increased electrical and physical effects associated with dense interconnects and closely packed transistors. Achieving timing, power, SI, and DFM closure for the most complex SoC designs presents an unprecedented number of challenges to ASIC design teams.

Achieving Low Power consumption in 65nm/40nm/28nm technologies is one of the top priorities for countless applications and has led to various innovative solutions including multi-Vdd, multi-Vt, on/off power domains, integrated clock gating (ICG), power aware place/route, and IR-drop aware STA methodologies. Such solutions present a set of unique challenges in physical implementation arena.

High Performance in the sub-40nm era means not only achieving speed objectives for your design but also striking the right balance between design constraints such as power, timing, and area.

SoC design size and complexity are quickly approaching hundreds of million gates. Because today’s EDA tools are not equipped to deal with such complexity and size, it is often required to employ various innovative hierarchical physical implementation methodologies.

Signal Integrity issues are tied to many areas such as power, timing, and DFM. Trying to manage SI issues later in the design cycle can be time consuming and can lead to a non-convergent path. Proactive measures should be taken during earlier stages of physical implementation flow to guarantee SI closure.

Design for Manufacturing (DFM) is a major issue in sub-90nm designs due to increasing complexities with process variability. Strict nanometer process constraints and ever more intractable optical lithography challenges make yield management a major design obstacle, not just simply a manufacturing concern.

Sub-40nm IC design challenges require tool expertise, experienced engineers, and efficient methodologies. The Uniquify team recognizes and understands all sub-90nm challenges and offers innovative solutions for leading edge ASIC designs. We work closely with customers to ensure physical implementation is seamless, delivering high quality products on time to guarantee first-time working silicon.

"Nethra Imaging procured Uniquify’s SoC design services and DDR3 IP for our highly complex SoC designs because of their proven and disciplined 65nm/40nm ASIC methodology, Perseus. Uniquify’s dedicated team exceeded our expectations by meeting our stringent tapeout schedule and implementing all complex SoC requirements. "
Ramesh Singh, President & CEO, Co-Founder, Nethra.