Uniquify, Inc. is a privately held, rapidly growing system-on-chip (SoC) design, integration and manufacturing services supplier, and innovative developer and provider of high-performance adaptive IP. Our “ideas2silicon” services range from spec development and front-end design through physical design to delivery of packaged, tested chips. Uniquify’s San Jose headquarters is its primary design center but additional design teams are headquartered in Vietnam, India, Korea, Japan, and China.
Job Description The Sr. IC Packaging Engineer will provide project management, package design/development and support for high performance IC or semiconductor assemblies, and/or completed units.
The individual will be responsible for influencing the architecture/design, materials selection and structural integrity of high performance IC packages and other associated components and collateral’s under manufacturing, test and usage conditions.
Focus on package layout design, SI/PI analysis and testing of microelectronic packages. Is expected to identify, assess and/or develop key analytical techniques to enable/suggest package vendors to improve various electrical performance. As part of the job function, candidate will also be expected to interact with other engineers/vendors/contractors to define and execute validation experiments as part of package design process.
Qualifications The ideal candidate should possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.
The candidate must possess a BS/MS in Mechanical / Mechanics / Electrical / Material Engineering, or a related discipline
~7+ years of experience in electronics packaging in related environment
Solid technical understanding of full range of PCB technology, semiconductor packaging materials
Practical experience of substrate layout design with high speed interface such as Serdes over 3+Gpbs with multiple layers ~ 10
Deep knowledge of Signal integrity analysis and power analysis for various high speed interface such as Serdes is a must
Knowledge of package qualification and reliability methods and failure analysis is a plus
Excellent communication skills
Applicants must have a legal right to work in the US without sponsorship
Willingness to travel internationally
IC Packaging & PCB technologies, system design
Job Type Full time; local candidates only
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ASIC Design (DFT) Engineer Internship
We are seeking sharp and highly motivated candidates whom our experienced ASIC design team can teach and train into an excellent ASIC design engineer. Candidate will work closely with our industry experienced physical design & DFT ASIC team developing multi-million gate state of the art System-on-Chip (SoC) designs. Candidate will gain understanding and assist in the development effort including but not limited to DFT, synthesis, simulation and verification, static timing analysis as well as physical implementation and verification. This is a great opportunity for anyone who wants to start a career in the ASIC design industry.
A Bachelor’s degree or higher in Electrical Engineering or Computer Engineering
Experience with a scripting language such as TCL, Perl, and/or Make
Strong analytical and critical thinking skills
Good communication skills and ability to work in a team environment
Experience with Verilog coding and verification is a plus
Project or industry experience in ASIC is a plus
Course work in digital IC design a plus
Must be legally authorized to work in the United States without sponsorship