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In The News

Video interview of Graham Bell of Uniquify by Warren “Big Data” Savage, GM IP at Silvaco on career path, DDR IP update, SoC products, 22FDX, and standards.– Take5 YouTube channel – November 2017

Video interview of Graham Bell on “Uniquify at DAC 2017: New LPDDR 4 IP in silicon production and 22nm GF FDX FD-SOI Partnership” – Design-Reuse.com – June 2017

Video interview by EDACafe.com at DAC 2017 on “New LPDDR 4 IP in silicon production and 22nm GF FDX FD-SOI Partnership” – Graham Bell – June 2017

“Will adaptive IP meet the low-power IoT challenge?” – Graham Bell – Embedded Computing Design – June 2017

“The Intricate Puzzle Known as Chip Design” – Bob Smith – ChipDesign.com – 2014

“Respect to the Customer: Uniquify’s Bob Smith offers rational advice” – Bob Smith – EDACafe.com -2014

“DAC 2014 IP Talks!” – Bob Smith – ChipEstimate.com – 2014

“IP Integration: Not a Simple Operation” – Contributions by Bob Smith – Chip Design 2014

“Internet of Things (IoT) and EDA” – Contributions by Bob Smith – Chip Design 2014

Interview with Josh Lee addressing DDR and Self Calibrating Logic – Electronic Design – 2014

The “Bitcoin Blitzkrieg,” Uniquify and the Bitcoin Boom – Bob Smith interview with Amelia Dalton – Fish Fry 2014

Uniquify’s “Game-Changing DDR Memory IP” explained by Bob Smith – Tech Talks – ChipEstimate.com 2014

Bob Smith of Uniquify writes that “Design Management System Eliminates ASIC Shortcut Risk” – Embedded Computing Design

Uniquify’s Bob Smith DDR IP Interview with Amelia Dalton on The Fish Fry at DAC 2013 – EE Journal

Uniquify’s Josh Lee on “Adaptive IP is the wave of the future” – EE Times

Uniquify’s Josh Lee on “Shaking Up the Design Services Market a la Amazon” – EE Times

Uniquify’s Josh Lee on “What Designers Can Expect with DDR4 SDRAM” -Embedded Computing Design

Uniquify’s Josh Lee writes on “Consumer Electronic Demand Driving Fundamental Shifts in Semiconductor Design and Intellectual Property” GSA Forum – March 2012

Silicon Valley Startup Granted US Patent on Critical DDR2/DDR3 Timing Innovation for Chip Designs – Design and Reuse

Memory controller IP enables timing closer, higher yield – EE Times Asia

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  •   USTR2100 TCON
  •   USTV3000 TCON
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  •   USN8300 Uplink Controller

Design IP

  • DDR Interface
  • SerDes
  • Cryptography and Memory

SoC Services

  • Architect, Design and Implement
  • Custom IP Design and Hardening
  • Fabless Manufacturing

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+1-408-235-8810

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