From the inception in 2005 in San Jose, CA, Uniquify has been a leader in SoC design, services, and innovation IP addressing 100’s of SoC tape-outs on advance technology node such as 7nm from foundries, TSMC, Global Foundries, Samsung, UMC, and SMIC. Capabilities of Uniqiufy’s global SoC team spans from spec, RTL design and verification, Physical design and verification, supply-chain management, packaging and testing, and production ramp.
Seraphim is knowledge based SoC platform that Uniquify has been developing and employing over the past 17 years that automates physical design flow, boosts engineers’ capacity and capability, fixes EDA tool deficiencies, implements QoR analysis automation, enables global team management, and streamlines PD resource training and scaling in any design center around the world.
Seraphim automates entire SoC physical design flow to eliminate errors and inefficiencies introduced by manual work performed by engineers to reduce execution time & resources, ensures repeatability and convergence, guarantees the correct-by-construction design flow, eliminates any changes without documentation, and accelerates final tape-out cycle to reduce the overall time to market. Areas of SoC automation by Seraphim include data & library management, tool and flow scripts, QoR analysis, and team management and control.
Seraphim is a complete SoC platform addressing, flow automation, EDA deficiency elimination, analysis automation, and global team management, it is used to train, deploy, and scale PD team anywhere in the world by shortening training cycle by 5x, boosting individual engineer’s capacity by 3x, and streamlining remote team management. Uniquify has been utilizing Seraphim SoC Platform to train, deploy, and manage SoC teams around the globe in the US, Vietnam, and India.
Every design strategy chosen by an Engineer is documented and can easily be monitored. Both an individual engineer’s progress as well as the entire team’s development throughout a project. All SoC environments are unified and organized allowing Quality of Results to be assessed quickly. From Place and Route to Static Timing Analysis or Physical Verification, all stages can be monitored in a single location.
There are challenging issues and inherent tool deficiencies in complex SoC designs and flows ranging from top and block level implementation, library and design data management, and tool limitations. Seraphim addresses these issues and deficiencies by parameterized and automated design methodology that is flexible and reusable by any engineer and team.
Analyzing QoR reports, tool log files, and various output files are paramount important for engineers to adjust and strategize their next move to ensure convergent SoC execution. Many engineers can get overwhelmed and bogged down by the shear amount of analysis that they need to perform each iteration of design flow. Seraphim analysis automation ensures each engineer to fully digest all reports, log and output files to make the “right moves” to bring design closure in a consistent and convergent manner.
One example of the type of analysis that Seraphim will provide is the Buffer & Inverter Efficiency Report. For critical paths, Seraphim will show the average distance per delay unit that each buffer or inverter is providing.
In Post-Route STA cell analysis , Seraphim can parse the lib files and analyze whether a cell is optimized well based on its capacitance and transition from the STA reports.